In a Thin Film Transistor (TFT) liquid crystal display device in the prior art, pixels are controlled separately and precisely by active switches, so a finer display effect can be achieved as compared with previous passive driving techniques.
Scan lines of a display panel have some impedance. The impedance of a scan line in a TFT drive circuit may be represented by a multitude of series RC circuits, as illustrated in FIG. 1.
Ideally, when a scan signal is loaded to a scan line from an input end of the scan line, there is a waveform diagram of the scan signal as illustrated in FIG. 2A, where a TFT is turned on at a time t1 and turned off at a time t2. In practice, the series RC circuit equivalent to the scan line in FIG. 1 may cause a delay distortion of the scan signal during transmission of the scan signal, thus resulting in a waveform diagram of the distorted scan signal as illustrated in FIG. 2B, where the TFT is turned on at the time t1 and turned off at a time t2′ with t2′>t2, and as can be apparent, there is a delay distortion occurring at the time when the TFT is turned off. Moreover, the extent of the delay distortion of the scan signal is so variable during transmission of the scan signal that the closer the location is to an end of the scan line, the higher the equivalent impedance of the series RC will be, and the more serious the delay distortion of the scan signal will be.
In the existing liquid crystal display device, the delay distortion of the scan signal may degrade the display quality and result in area flickering, crosstalk and other problems.
At present, there are the following three common scan line design schemes:
1. Unilateral driving as illustrated in FIG. 3A, where this scheme is simple to design but may suffer from the delay distortion described above and other problems.
2. Bilateral driving as illustrated in FIG. 3B, where this scheme can improve the delay distortion but may be complex to design a circuit and strictly require synchronization of a clock signal and also suffer from increased power consumption, lowered reliability and other problems.
3. Interlaced driving as illustrated in FIG. 3C, where this scheme can visually improve the problems (e.g., flickering, crosstalk, etc.) arising from the delay distortion but fails to substantially improve the delay distortion; and additional clock signals for interlaced driving may result in an increased load on a drive integrated circuit.